Lab 3
Your goal for this lab is to design a circuit that implements a 3-input logic gate that implements Z=¬(C(A+B)) where the ¬ symbol stands for logical negation. This function is enumerated in the following truth table:
C B A | Z
=========
0 0 0 | 1
0 0 1 | 1
0 1 0 | 1
0 1 1 | 1
1 0 0 | 1
1 0 1 | 0
1 1 0 | 0
1 1 1 | 0
The schematic diagram below includes the resistive pullup for the logic gate and some voltage sources that serve as the power supply and generators for the signals that will be the inputs to the gate. The voltage sources generate the three input signals (A,

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That's the diagram for the implementation of the output Z.

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