Here's the question you clicked on:
AdJ
design a circuit that implements a 3-input logic gate that implements Z=¬(C(A+B)) where the ¬ symbol stands for logical negation
tw0 m0sfets with inputs A & B in parallel and a m0sfet with input C shall be in series with the ab0ve parallel c0mbinati0n
|dw:1349197904504:dw|
@kashyap : pmos part of your ckt shud also b dere
Pm0s secti0n w0uld have been there if the questi0n w0uld menti0n CM0S techn0l0gy ... f0r the MIT c0urse , this is right !!