anonymous
  • anonymous
design a circuit that implements a 3-input logic gate that implements Z=¬(C(A+B)) where the ¬ symbol stands for logical negation
MIT 6.002 Circuits and Electronics, Spring 2007
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SOLVED
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chestercat
  • chestercat
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anonymous
  • anonymous
tw0 m0sfets with inputs A & B in parallel and a m0sfet with input C shall be in series with the ab0ve parallel c0mbinati0n
anonymous
  • anonymous
|dw:1349197904504:dw|
anonymous
  • anonymous
|dw:1349273509655:dw|

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anonymous
  • anonymous
@kashyap : pmos part of your ckt shud also b dere
anonymous
  • anonymous
Pm0s secti0n w0uld have been there if the questi0n w0uld menti0n CM0S techn0l0gy ... f0r the MIT c0urse , this is right !!

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