A community for students.
Here's the question you clicked on:
 0 viewing
Abhaypratap
 2 years ago
Need Help for Lab 6
please ...
Abhaypratap
 2 years ago
Need Help for Lab 6 please ...

This Question is Closed

kashyap
 2 years ago
Best ResponseYou've already chosen the best response.0me too stuck in the same ..

ali110
 2 years ago
Best ResponseYou've already chosen the best response.11. The final output voltage of the inverter when its input is high was measured to be ~193mv. The equivalent circuit for the inverter when the MOSFET switch is on is a voltage divider with a pullup resistance of RL and a pulldown resistance of RON. The voltage‐divider equation for the output voltage is .193 = VSRON/( RON + RL) = 3RON/(RON + 10000) Solving for RON gives 689Ω. 2. VTH = VSRON/(RON + RL) = .193V RTH = RON  RL = 643Ω 3. Equation 10.66 is vC (t) =VTH +(VS −VTH )e−t/RTHCGS which, after substituting the known values becomes.25 =.193+(3−.193)e−t/(643⋅2⋅10−13 ) . Solving for t gives t = −(643)(2 ⋅10−13 ) ln .25−.193 3−.193 # $ % & ' ( =.5011⋅10−9 , i.e., about 0.5ns. 4. The measured value for tpd,0→1 is 0.6ns. 5. The measured value for tpd,1→0 is 3.45ns. Substituting the known values into Equation 10.71 gives 2.5 = 3+(.193−.3)e−t/(10000⋅2⋅10−13 ) , which, when solved for t gives 3.4505ns. The plot from the transient analysis of the ring oscillator is shown below with the start and stop times of one cycle as indicated (measurements at any given point in two successive cycles gives a similar result). The estimate for both transitions is (31.375ns – 15.125ns)/9 = 1.8ns. From questions 4 and 5: tpd,0→1 + tpd,1→0 = 4.15ns which is the conservative worst‐case time for two transitions, almost a factor 3 longer!

ali110
 2 years ago
Best ResponseYou've already chosen the best response.1for The circuit below contains an inverter designed to be used in a system where VS=3V, VOL=0.25V and VOH=2.5V. The input to the inverter is hooked to a voltage source that makes a 0→1 transition at t=0. The performance of the inverter is measured as it drives a 200fF capacitive load, which represents the parasitic capacitance of the wiring and the inputs of other logic gates hooked to the output of the inverter.

Abhaypratap
 2 years ago
Best ResponseYou've already chosen the best response.0thanks a lot for your help :)
Ask your own question
Sign UpFind more explanations on OpenStudy
Your question is ready. Sign up for free to start getting answers.
spraguer
(Moderator)
5
→ View Detailed Profile
is replying to Can someone tell me what button the professor is hitting...
23
 Teamwork 19 Teammate
 Problem Solving 19 Hero
 Engagement 19 Mad Hatter
 You have blocked this person.
 ✔ You're a fan Checking fan status...
Thanks for being so helpful in mathematics. If you are getting quality help, make sure you spread the word about OpenStudy.