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The drain of Q1 is still high and the gate of Q2 is at VOL. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to charge the gate capacitance of Q2 to VOH? incorrect Note: In fact, the SR model is not very accurate for Q3 in this circuit because Q3 is in saturation, but use the SR model anyway, for simplicity. Now, suppose DIN is high, the drain of Q1 is low, and the gate of Q2 is at VOH. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to discharge the gate capacitance of Q2 to VIL?
VS=5.0V, VOH=3.5V, VIH=3.0V, VIL=0.9V, VOL=0.5V The gate-source capacitance CGS=3.5fF and VT=1.0V. RON=2150.0Ω, ROFF=95.0MΩ and RPU=18.0kΩ.
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@NURALI CAN U LEMME KNO MY ANSWER We assume an "ancient" 1μm technology satisfying the static discipline: VS=5.0V, VOH=3.5V, VIH=3.0V, VIL=0.9V, VOL=0.5V The gate-source capacitance CGS=3.5fF and VT=1.0V. RON=2150.0Ω, ROFF=115.0MΩ and RPU=10.0kΩ.
We assume an "ancient" 1μm technology satisfying the static discipline: VS=5.0V, VOH=3.5V, VIH=3.0V, VIL=0.9V, VOL=0.5V The gate-source capacitance CGS=3.5fF and VT=1.0V. RON=2150.0Ω, ROFF=110.0MΩ and RPU=16.0kΩ.