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lunarka

  • 2 years ago

can anyone help me with H8p3 last question please?

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  1. axi
    • 2 years ago
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    24

  2. lunarka
    • 2 years ago
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    i put it, but still didnt get green mark :(

  3. axi
    • 2 years ago
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    give me d complete ques?

  4. sandeep122443
    • 2 years ago
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    can u pls anwer the question before dat i mean last 2nd question

  5. andrew.winney
    • 2 years ago
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    the one befor t s 45!!

  6. axi
    • 2 years ago
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    75

  7. Nurali
    • 2 years ago
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    tell me question

  8. andrew.winney
    • 2 years ago
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    Now, suppose DIN is high, the drain of Q1 is low, and the gate of Q2 is at VOH. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to discharge the gate capacitance of Q2 to VIL?

  9. andrew.winney
    • 2 years ago
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    We assume an "ancient" 1μm technology satisfying the static discipline: VS=5.0V, VOH=3.5V, VIH=3.0V, VIL=0.9V, VOL=0.5V The gate-source capacitance CGS=3.5fF and VT=1.0V. RON=2050.0Ω, ROFF=95.0MΩ and RPU=10.0kΩ. The specifications for this logic family say that we have to refresh this memory every 64ms. So, if we charge the gate capacitance to VOH it will take more than 64ms to decay to VIH.

  10. nickfrei
    • 2 years ago
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    for 4 use (-ln( (3.5-5) / (0.5-5) ) * (RPU+RON) * 3.5*10^-15) * 10^12

  11. 1431mahi
    • 2 years ago
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    for 4th (-ln( (3.5-5) / (0.5-5) ) * (RPU+RON) * 3.5*10^-15) * 10^12 for 5th (-ln( (0.9-(5*RON/(RON+RPU))) / (3.5-(5*RON/(RON+RPU))) ) * ((RON|| RPU) + RON) * 3.5*10^-15) * 10^12 got ryt give me best response

  12. namitha_s
    • 2 years ago
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    @1431mahi: there is a bracket extra in ur ans 4 5th question..

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