there's something called setup time and hold time for a circuit.......
what if the length of clock is less than any of these times?
what would the output be?
MIT 6.002 Circuits and Electronics, Spring 2007
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setup time is the amount of time, the data has to be held stable before active clock edge.
hold time is the amount of time, the data has to be held stable after active clock edge.
to avoid setup time violations:
clock period > ff propagation delay + combi logic delay + setup time + max clock skew.
so with your scenario setup time violation occurs and hence metastable state.
to avoid hold time violations:
hold time <= ff prop delay + combi logic delay - max clock skew
from the equation hold time doesnot depend on clock period.
but still with your scenario... there are chances that there will be timing violations in the subsequent paths