• ganeshie8
how does a two flop synchronizer work ? i get the metastability part of it, but im not getting clue how we make sure we capturing the actual incoming async data, and not just some metastable stabled high/low value ?
  • chestercat
I got my questions answered at in under 10 minutes. Go to now for free help!
At vero eos et accusamus et iusto odio dignissimos ducimus qui blanditiis praesentium voluptatum deleniti atque corrupti quos dolores et quas molestias excepturi sint occaecati cupiditate non provident, similique sunt in culpa qui officia deserunt mollitia animi, id est laborum et dolorum fuga. Et harum quidem rerum facilis est et expedita distinctio. Nam libero tempore, cum soluta nobis est eligendi optio cumque nihil impedit quo minus id quod maxime placeat facere possimus, omnis voluptas assumenda est, omnis dolor repellendus. Itaque earum rerum hic tenetur a sapiente delectus, ut aut reiciendis voluptatibus maiores alias consequatur aut perferendis doloribus asperiores repellat.

Get this expert

answer on brainly


Get your free account and access expert answers to this
and thousands of other questions

  • ganeshie8
  • anonymous
you need to understand the Mean Time Between Failures (MTBF) concept to understand the synchronization part. The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. this approach can not guarantee that metastability cannot pass through the synchronizer; they simply reduce the probability to practical levels. The metastability occurrences can be predicted by using the mean time between failures . C1 and C2 are constants that depend on the technology used to build the flip-flop; tMET is the duration of the metastable output; and fclk and fdata are the frequencies of the synchronous clock and the asynchronous input, respectively. please look ate mtbf.bmp for formula. Designers can use special metastable hardened flops for increasing the MTBF. For example, in sync_Fig1.bmp, a synchronizer flop is used following the signal DB. So, instead of the metastable signal DB being used in the function downstream as in sync_Fig2.bmp, the stable signal DB2 is used in the logic downstream.

Looking for something else?

Not the answer you are looking for? Search for more explanations.