anonymous
  • anonymous
How do you know when to add the an inverter to the output of a complex CMOS logic gate? I always go directly to the pull down network, then take the dual for the pull up network, but then I usually add the inverter; But some examples I have seen do not do this.
MIT 6.002 Circuits and Electronics, Spring 2007
chestercat
  • chestercat
I got my questions answered at brainly.com in under 10 minutes. Go to brainly.com now for free help!
At vero eos et accusamus et iusto odio dignissimos ducimus qui blanditiis praesentium voluptatum deleniti atque corrupti quos dolores et quas molestias excepturi sint occaecati cupiditate non provident, similique sunt in culpa qui officia deserunt mollitia animi, id est laborum et dolorum fuga. Et harum quidem rerum facilis est et expedita distinctio. Nam libero tempore, cum soluta nobis est eligendi optio cumque nihil impedit quo minus id quod maxime placeat facere possimus, omnis voluptas assumenda est, omnis dolor repellendus. Itaque earum rerum hic tenetur a sapiente delectus, ut aut reiciendis voluptatibus maiores alias consequatur aut perferendis doloribus asperiores repellat.

Get this expert

answer on brainly

SEE EXPERT ANSWER

Get your free account and access expert answers to this
and thousands of other questions

anonymous
  • anonymous
Depends on your approach either way is ok. but its always good to think in terms of number of transistors being used. say u have (ab+cd')' its dual will be (a'+b')(c'+d). compare the number of transistors used in both the implementations and decide which one will uses lesser number. because when you are actually working on a chip design, even a single transistor will effect the design

Looking for something else?

Not the answer you are looking for? Search for more explanations.