i was reading the concept of pipelining
and it was mentioned that we need to put some Intstruction registers in b/n different stages of a pipeline
can any1 xplain me the need for these Instruction registers?
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where did u read that?week12?(if that is so i havent seen any week 12 vids yet sry)
Well pipelining means we are putting some tasks in queue, and in the processor world the tasks are represented by "the instruction register" (it holds the command which needs to be executed on the processor)
Although it was a very naive answer, tell me if you were asking something different.
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Take for example the following five-stage pipeline: http://www.cc.gatech.edu/~hyesoon/fall09/pipeline_lab1.jpg
There are five stages: IF (or FE), ID, EX, MEM and WB. Suppose you have to instructions: one and two.
Instruction one starts in the IF stage. The next cycle, one will go to the ID stage and two will start in the IF stage. This cycle, two is read from the memory, but instruction one should also be remembered (since it cannot be read from memory, 'cause the memory is busy with two). That's what the registers (latches in the figure) between the stages are for.