A community for students.
Here's the question you clicked on:
 0 viewing
malihe
 3 years ago
can anybody tell me please how to design 4_bit fulladder with half adder with verilog?
malihe
 3 years ago
can anybody tell me please how to design 4_bit fulladder with half adder with verilog?

This Question is Closed

praveenroyg
 3 years ago
Best ResponseYou've already chosen the best response.1// full adder verilog code using half adder starts here //===================================================== module full_adder_inst ( p_in, q_in, carry_in, fullsum_out, fullcarry_out); input p_in, q_in, carry_in; output fullsum_out, fullcarry_out; wire sum_wire; wire carry_wire; wire sum_wire1; wire carry_wire1; half_adder instance1 ( .a_in( p_in) , .b_in( q_in), .sum_out( sum_wire), .carry_out( carry_wire) ); half_adder instance2 ( .a_in( sum_wire), .b_in( carry_in), .sum_out( sum_wire1), .carry_out( carry_wire1) ); assign fullsum_out = sum_wire1; assign fullcarry_out = carry_wire  carry_wire1; endmodule

praveenroyg
 3 years ago
Best ResponseYou've already chosen the best response.1module full_adder ( p_in, q_in, r_in, s_in, a_in, b_in, c_in, d_in, carry_in, sum_out1, sum_out2, sum_out3, sum_out4, carry_out); input p_in, q_in, r_in, s_in, a_in, b_in, c_in, d_in, carry_in; output sum_out1, sum_out2, sum_out3 ,sum_out4, carry_out ; wire sum_wire; wire carry_wire; wire sum_wire1; wire carry_wire1; wire sum_wire2; wire carry_wire2; wire sum_wire3; wire carry_wire3; full_adder_inst instance1 ( .p_in(p_in), .q_in(q_in), .carry_in(carry_in), .fullsum_out(sum_wire), .fullcarry_out(carry_wire)); full_adder_inst instance2 ( .p_in(r_in), .q_in(s_in), .carry_in(carry_wire), .fullsum_out(sum_wire1), .fullcarry_out(carry_wire1)); full_adder_inst instance3 ( .p_in(a_in), .q_in(b_in), .carry_in(carry_wire1), .fullsum_out(sum_wire2), .fullcarry_out(carry_wire2)); full_adder_inst instance4 ( .p_in(c_in), .q_in(d_in), .carry_in(carry_wire2), .fullsum_out(sum_wire3), .fullcarry_out(carry_wire3)); assign sum_out1 = sum_wire; assign sum_out2 = sum_wire1; assign sum_out3 = sum_wire2; assign sum_out4 = sum_wire3; assign carry_out = carry_wire3; endmodule

praveenroyg
 3 years ago
Best ResponseYou've already chosen the best response.1// half adder verilog code starts here //====================== module half_adder (a_in, b_in, sum_out, carry_out); input a_in, b_in; output sum_out,carry_out; assign sum_out = a_in ^ b_in; assign carry_out = a_in & b_in; endmodule // half adder verilog code ends here //=====================

praveenroyg
 3 years ago
Best ResponseYou've already chosen the best response.1this will be your desired design
Ask your own question
Sign UpFind more explanations on OpenStudy
Your question is ready. Sign up for free to start getting answers.
spraguer
(Moderator)
5
→ View Detailed Profile
is replying to Can someone tell me what button the professor is hitting...
23
 Teamwork 19 Teammate
 Problem Solving 19 Hero
 Engagement 19 Mad Hatter
 You have blocked this person.
 ✔ You're a fan Checking fan status...
Thanks for being so helpful in mathematics. If you are getting quality help, make sure you spread the word about OpenStudy.