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  • 2 years ago

can anyone tell me please how to design 4_bit full adder with half adder by verilog?

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  1. dfordivam
    • 2 years ago
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    First create a module for the half adder, then use two half adders to create the full adder. You may then combine as many full adders as you want. depending upon your requirements the half adder may be behavioral or structural. So the complete thing will look like module half_adder (a , b, o){ ... } module full_adder(a, b, o){ half_adder ha1(...); half_adder ha2(...); } module 4_bit_full_adder(...){ full_adder fa1(...); full_adder fa2(...); full_adder fa3(...); full_adder fa4(...); }

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