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Do they want yo to convert it to phasors?
How would you draw a diagram without any for the impedences?
I think so, yes, we need to draw the graph.
I looked on YouTube at a video which showed how to draw the phase diagram for a series circuit, but I didn't understand how to do it for parallel circuits.
give me a sec.
sorry, i had to do something real quick.
but ye, Vc would be in the middle between the two, because that's the same as source.
so Vc = impedance of capacitor * i2. Vr = Ri1. VL = impedance of inductor * i1
Sorry, actually I believe the voltage of capacitor would come down diagonally. |dw:1433844208827:dw|
Thanks for answering, I'll try to understand it.
If I'm to understand the circuit. I see a series arrangement of an inductor L and resistor R. Further, this series arrangement is in parallel with a single capacitor C, and the complete circuit in parallel with the applied voltage u. Current I is the source current and will be the resultant (phasor) of I1 and I2. I1 is the current in the series arrangement, and I2 is the capacitor current (I am assuming AC). I hope this is the way you see it also.
first I would draw a phasor diagram for the series leg, using I1 as the reference phasor.|dw:1433858566609:dw|Note the Vr would be in phase with I1, but the VL would lead the current I1 by 90 degrees. (remember ELI the ICE man). The resultant voltage of that combination of Vr and VL will result in a voltage "leading" I1 by something less than 90 degrees. Or we can say the current is "lagging" by less than 90 degrees as it is an inductive circuit.
Now looking at the entire circuit which is in parallel. We will use voltage as our reference. This is because the voltage across each leg is the same (v), Using voltage as a reference and showing I2 relationship to (V), our diagram looks like this:|dw:1433859228804:dw|It is important to note that the magnitudes of I1 and I2 cannot be determined as no info was provided regarding the reactance of L and C (Xc and Xl) But we can see that I will be the combination (resultant phasor) of I1 and I2 and whether I will lead or lag will depend on the reactance. Assuming the reactances and resistance were all the same value it could look like this:|dw:1433859615247:dw| The over all circuit would appear capacitive with current leading the voltage by less than 90 degrees. With appropriate values, the circuit could appear resistive (with capacitive and inductive currents cancelling each other) then in this case V and I would be in phase.
This has been "wordy" but there is a lot of assumptions which can be made as well as many variations of a "phasor diagram"
Just in case you haven't heard of "ELI the ICE man" it is a memory trick to remember in a capacitor I (current) C (capacitor) E (electromotive force or current I is leading E and ELI (E-voltage, L-inductor, I-current) voltage leads current.
Wow, thanks a lot, radar! I'll have a serious look at what you posted, and, hopefully, I'll be able to understand how to solve this kind of problem.