anonymous
  • anonymous
8 Bit Shift Register VERILOG Hello, how come I can't assign the output pins to my q register in pin planner? //8Bit shift register module L4P6(q, clk, data); input data; input clk; output reg q; reg q0, q1, q2, q3, q4, q5, q6; always @(posedge clk) begin q0 <= data; q1 <= q0; q2 <= q1; q3 <= q2; q4 <= q3; q5 <= q4; q6 <= q5; q <= q6; end endmodule
Engineering
  • Stacey Warren - Expert brainly.com
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SOLVED
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katieb
  • katieb
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anonymous
  • anonymous
I'm using quartus, I'm able to assign the output for q but not the rest of the actual register.

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